A Class AB CMOS amplifier was introduced by Callewaert and Sansen in an article entitled “Class AB CMOS Amplifiers with High Efficiency” in the IEEE Journal of Solid State Circuits, Vol. 25 No. 3, 1990 (incorporated herein by reference). Their circuit is shown in its simplified schematic in FIG. 1.
In the original paper, the authors discussed that maximum current amplification during transition periods could easily exceed 25. However, much has changed since this prediction was made in 1990. Short channel effects coupled with a much lower power supply have restricted this ratio to a maximum of 15. Present implementations more typically have an actual current amplification of about 12.
The operation of the Callewaert and Sansen Class AB circuitry is described in detail in their article, but will be generally summarized here as well.
FIG. 1 shows a Class AB amplifier 10 in accordance with the principles of Callewaert and Sansen. In FIG. 1, transistors Q1-Q9 define an input stage 12. Within the input stage 12, transistors Q1, Q2, Q3, Q4, Q5, and Q6 define a differential stage 14. The differential stage 14 includes a differential pair defined by transistors Q2 and Q5, having respective gates defining inputs vn and vp.
Transistors Q10, Q11, Q12, Q13, Q14, Q15, Q16, Q17, and Q18 define a complementary input stage 18 having PMOS transistors Q11 and Q14 as the inputs.
Transistors Q20 and Q19, connected to p4 and n2, define an output stage 20.
The general principle behind a Class AB amplifier is that in steady state, when no switching occurs, the amplifier consumes a relatively low operating current. But when a transition occurs, the Class AB amplifier requires some sort of mechanism to inject a current so that a load capacitance can be charged or discharged very quickly. After settling, and a return to steady state, the Class AB amplifier is again in a low current mode.
In FIG. 1, transistor Q9 is connected as a current source, as p1 is coupled to a DC bias. Similarly, transistor Q18 is connected as a current source. FIG. 2 is a simplified circuit schematic showing these transistors as current sources. FIG. 2 is similar to FIG. 1, like reference numerals indicating like components.
Referring to FIG. 2, when input voltage vn is higher than input voltage vp, there is an increase in current through transistor Q2 and a decrease of current through transistor Q5. Transistor Q3 is connected as a diode.
The increase in current in transistor Q2 also goes through transistor Q3, which then gets mirrored to transistor Q4. Because the current of transistor Q5 is reduced, the excess current has to go somewhere, so it travels through path p5, and goes down through transistors Q8 and through Q7. Voltage at the gate p2 of transistor Q8 is set at some steady state bias reference voltage. The bias generator is not shown here, but it will provide a DC bias.
When the current through transistor Q7 increases, the voltage at node n2, the gate of transistor Q7, increases. Node n2 is also connected to the gate of output transistor Q19. Therefore, there is a sudden increase in current on the output transistor Q19 when the current through transistor Q7 increases.
As mentioned above, transistor Q9 (see FIG. 1) acts as a constant current source. Therefore, in steady state, all the current through transistor Q9 ideally goes through transistor Q7. The current through Q4 goes through Q5, and the current through Q3 goes through Q2.
Circuitry 18 is complementary to circuitry 12 and has a differential stage 22, and a current sum branch or stage 24. The differential stage 22 includes a differential pair of transistors Q11 and Q14 that are p-type transistors. When the input voltage vp goes above input voltage vn, there is an increase in current through transistor Q11, which increases the current through transistor Q12. Transistor Q12 is mirrored to transistor Q13, and that excess current goes through transistor Q16. Transistor Q16 is mirrored to transistor Q20, as the gate voltage p4 of transistor Q16 is coupled to the gate of transistor Q20. Transistor Q20 provides the output out when vp goes above vn. Thus, the operation of circuitry 18 is complementary to the operation of the circuitry 12.
In FIG. 2, the differential stage 22 including PMOS differential pair Q11 and Q14 controls an PMOS output Q20, affecting the value of the output “out” in FIG. 2, and the differential stage 14 including NMOS differential pair Q2 and Q5 controls an NMOS output Q19, affecting the value of the output “out.” Each one of the differential stages 14 and 22 controls one of the output transistors Q20 and Q19.